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The vastep Command

This command has application when simulating a circuit containing Verilog block, and the option vastep has been set to 0. In this case, a call to this command will advance the Verilog simulation to the next clock tick. This function can be called from a callback initiated from a .stop line, used when co-simulating Verilog and SPICE.

Stephen R. Whiteley 2022-09-18