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Technology File Layer Block Keywords: Extraction

This section describes the keyword entries which appear in layer blocks which categorize the purpose of the layer for extraction. These define the conductor layers which are involved in grouping, identify vias between conductors, etc. These keywords can appear only in physical layer fields.

All of these settings can be entered with the Edit Tech Params command in the Attributes Menu and then written to disk with the Save Tech command in the Attributes Menu, or be entered with a text editor directly into the technology file.

Some of the keywords below use layer expressions, as were described in 15.1. A layer expression in its simplest form is a layer name. More generally, it consists of an expression involving layer names, the intersection operator (&), the union operator (|), and the inversion operator (!). Parentheses can be used to enforce precedence. These are the same type of expressions as used in the DRC tests. The expression is ``true'' at points where the expression would return opacity.

Conductor [Exclude expression]
This keyword indicates that the present layer is to be included in conductor net grouping. If the keyword Exclude and a following layer expression are given, the regions of the current layer under which the expression is true are clipped out for grouping purposes. For example, in CMOS technology a transistor is formed by a strip of CAA (active area) bisected by a CPG (polysilicon) gate. If ``Conductor Exclude CPG'' is given in the CAA layer block, the two pieces of CAA will be given separate group numbers, which is necessary to keep the transistor source and drain separate.

Routing [it route params]
This keyword implies that the layer is a conductor used for connecting between cells. The Conductor keyword is implied, so that the Conductor keyword does not also have to be supplied, unless there is an Exclude directive. Only layers with the Routing keyword given will be considered by the extraction system for connecting between cells, and cell formal terminals will only be assigned to Routing layers. This is not absolute, however. The extraction system will place formal terminals on Conductor layers under some circumstances, if necessary.

Optionally, routing parameter definitions may follow the keyword. These provide information to a third-party auto-route system, The parameters are saved in the Xic technology database, and are used when writing a technology file, but are not otherwise used directly by Xic. The recognized routing parameter definitions are listed below. These can appear in any order. These parameters will be parsed and set when reading the technology file, but can also be set when reading Cadence ASCII technology files.

This sets the preferred direction of routes on the layer. The ``dir='' is literal, and is followed by a letter or word, only the first letter of which is significant. If the first letter is H or X (case insensitive), the route direction is horizontal. If the letter is V or Y, also case insensitive) the routing direction is vertical. Otherwise, an error ensues.

This provides the values for the route pitch. Only the first letter of the ``pitch'' keyword need be present. This is followed by an equal sign (``=''), and one or two real numbers. The numbers are pitch values in microns. If there are two numbers, the first is the horizontal pitch, the second vertical, separated by a comma. Two numbers are required only if the horizontal and vertical pitch values differ.

This provides values for the route offset, and is parsed the same way as the pitch. The values are real numbers giving the offset in microns. The second number can be omitted if it is the same as the first. The offset is the routing grid origin relative to the cell origin.

This specifies the line width, in microns, used for routing. Presently, only one number is accepted, implying that horizontal and vertical routes have the same width.

This provides a maximum route length, in microns. A router may use this value to limit route lengths.

$\textstyle \parbox{4in}{\raggedright
{\sf GroundPlane}\\
{\sf GroundPlaneDark} (alias)\\
This keyword indicates that the present layer is to be treated as a clear-field ground plane. The layer is given the Conductor attribute. If the keyword ``Global'' appears, then every object on the layer will be assigned to the ground group 0. This would be appropriate if the layer represents a diffusion rather than a metallic ground plane. The default is to treat this level as a normal conductor, except that when this layer is grouped in the top-level cell, the group with the largest area is assigned to the ground group.

If ``Global'' is given, the GroundPlaneGlobal variable, which activates the mode, will be set.

Only one of the ground plane keywords can appear in the technology file. Conductor group 0 is used only if a ground plane has been specified. The ground plane layer can be referenced in Via and Contact lines just as any Conductor.

$\textstyle \parbox{4in}{\raggedright
{\sf GroundPlaneClear} [{\sf MultiNet} [0...
{\sf TermDefault} [{\sf MultiNet} [0$\vert$1$\vert$2]] (alias)\\
This keyword indicates that the present layer is to be treated as a dark-field ground plane. These keywords imply DarkField. Giving GroundPlane (or GroundPlaneDark) and DarkField is equivalent to GroundPlaneClear without MultiNet.

Only one of the ground plane keywords can appear in the technology file. Conductor group 0 is used only if a ground plane has been specified.

Without the MultiNet keyword, connections to this layer (as specified with the Via and Contact keywords), where this layer does not appear, are considered as connections to ground (group 0). Although this approach may work for simple cells, it can lead to trouble. Suppose that an island of ground plane metal is used as part of the metalization for the chip pads. This would appear as a hole in the displayed representation of the ground plane layer. Then each pad will be extracted as shorted to ground!

There is provision for more intelligent handling of the GroundPlaneClear layer, allowing the layer to be included in paths and groups. If the MultiNet keyword appears, the inverse of the layer is computed, and that (temporary) layer is used in the grouping. However, it can take quite a lot of behind-the-scenes computation if the GroundPlaneClear layer has complex patterning. Inversion is also done if the !set variable GroundPlaneMulti is given (note: this variable was formerly named HandleTermDefault). The temporary layer is treated as a clear-field ground plane, and all references to the ground plane will be applied to the temporary layer during grouping and extraction.

The name of the internal layer created is ``$GPI''. By default, this layer is invisible. It should not be directly edited by the user. The inverse layer is an internal layer and is never written to a file during conversion or a save. During extraction the GroundPlaneClear layer is ignored, and the inverse, which is a Conductor, is used to establish connectivity.

To establish connectivity for the commands in the Extract Menu, the inverse layer is created according to one of the algorithms described below. An optional integer 0-2 may follow the MultiNet keyword, which indicates the algorithm used for inversion. The algorithm can also be selected by setting the variable GroundPlaneMethod to an integer in the same range, with the !set command.

0 The inverted layer is created for each cell in the hierarchy by computing
$GPI = !GP & !$$
i.e., for each cell the ground plane is inverted and the areas over subcells are removed (recall that ``$$'' is a pseudo-layer representing subcell boundaries). This is the default.
1 The inverted layer is created only in the top cell in the hierarchy, and is the inverse of a flat representation of the ground plane layer from all cells in the hierarchy. The extraction algorithm will add virtual contacts from this layer to the appropriate places in the subcells.
2 The inverted layer is created in each cell of the hierarchy by creating a flat inverse of all of the ground plane found in the cell or lower in the hierarchy.

The default (0) method is the most efficient computationally, but the method will probably fail if sibling subcells overlap. In general, it is good practice to avoid cell overlap.

Method 1 will work if subcells overlap. However, since there is no local ground plane in the subcells, generating a netlist while in a Push (subedit) will not yield correct results.

Method 2 is the least efficient computationally, but each cell has a local ground plane.

Via layer1 layer2 [expression]
This keyword indicates that the present layer may provide connection points between conductor nets on layer1 and layer2. The layer1 and layer2 are names of layers each of which have the Conductor, Routing, or one of the GroundPlane keywords specified. In extraction, it is assumed that the via is formed by dark area on the present layer, and vias are completely covered by layer1 and layer2. A connection is indicated if the expression (which is a layer expression) is true at any point within the via. The Via keyword implicitly assigns DarkField. The recognition logic is as follows:

for each region of the Via layer {
if (there exists an object on layer1 that overlaps region)
if (there exists an object on layer2 that overlaps region)
if (there is no expression, or the area where expression is true in region is nonzero)
then the via indicates a connection between the two objects

If the expression is not given, it is always taken as ``true''.


Via M1 M2 !RES
A via is indicated if part of the via object on the present layer which is being evaluated is not covered by objects on RES.

Via M1 M2 I2
A via is indicated if the via object on the present layer is partially or completely covered with I2.

Via M1 M2 (!I2)&(!RES)
A via is indicated if part of the via object is not covered by I2 or by RES.

ViaCut expression
This is applied to an insulating layer with positive Thickness given, and defines cuts through the layer from the layer expression. This applies only when using three-dimensional processing such as for cross sections and the FastCap/FastHenry interface. It allows one to separate abstract (Thickness> not given or zero) Via layers from the physical layers that represent dielectrics. The abstract layers are used for netlisting, LVS, etc. The patterning is applied to the dielectric ViaCut layers when computing 3D geometry. This allows abstract vias to have cuts through multiple dielectric layers, which is required for some complex layer sequences.

Assume one has the following sequence of layers:

M1 I1A R1 I1B M2 VM12 VR12

The I1A and I1B layers are dielectrics, which encapsulate a resistor R1. VM12 is a via between M1 and M2, VR12 is a via between R1 and M2 (these are two separate etch steps).

To express this structure, one can use

PhysLayer M1
Thickness 0.2

PhysLayer I1A
ViaCut VM12
Thickness 0.2

PhysLayer R1
Thickness 0.1
Rsh 2.0

PhysLayer i1B
ViaCut VM12|VR12
Thickness 0.2

PhysLayer VM12
Via M1 M2

PhysLayer VR12
Via R1 M2

PhysLayer M2
Thickness 0.2

In this case, the VM12 and VR12 layers have no thickness, so they are abstract, but still establish connectivity for netlisting and LVS. The physical structure in 3D is actually established by the I1A and I1B layers, which must have nonzero Thickness. These are used when 3D extraction (cross section or L/C extraction) is being performed.

This keyword is intended to specify an explicit capacitor dielectric, which is different from a Via layer. A layer can not have both keywords. This is primarily to support the capacitance extraction interface. A Dielectric layer is assumed to be clear-field, unlike Via layers, though the DarkField keyword can also be applied. Also unlike Via layers, Dielectric layers are not assumed to be planarizing by default.

Contact layer [expression]
This keyword specifies that the present layer may be in contact with layer, which has the Conductor attribute, and is to be grouped accordingly in the wire net extraction. The expression (which is a layer expression), if given, must be true in the overlap region between the object and the objects on layer for contact to be established.

The purpose is to account for a contact metalization which is applied over the normal wiring layers, which may itself be used for making connections occasionally. The Contact keyword implies Conductor. The Contact keyword should be given in the layer block of the contact metal layer. It is not necessary (or desirable) to include a reciprocal Contact specification in the referenced layer's block.

This keyword indicates that the layer polarity on the chip is the reverse of that shown on-screen. This is usually the case for via layers, for example, which are rendered as small squares to indicate the contact location, which is actually a hole in an insulating layer. At present, the only command that uses this keyword is the Cross Section command in the View Menu. Layers with the keyword applied will be shown as on-chip in the cross sectional view. This keyword is implicitly assigned by both Via and GroundPlaneClear.

The keyword has a secondary effect if used in conjunction with the GroundPlane (or the equivalent GroundPlaneDark) keyword. The combination is equivalent to GroundPlaneClear.

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Next: Technology File Layer Block Up: Technology File Layer Blocks Previous: Technology File Layer Block   Contents   Index
Stephen R. Whiteley 2022-05-28