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## Connectivity Overview

Thus far we have described the basic methodology for producing a schematic. Armed with this information, users can quickly produce schematics of simple circuits. However, a lot has been skipped over, including the use of multi-conductor nets and vectorized instances. This section will review the basic connectivity concepts, and introduce these new topics.

Devices and subcircuits generally have ``pins'' which are hot-spots in the drawing where connection can occur. These hot spots may or may not be marked in the device or subcircuit symbol or schematic. In any case, pressing the terms button in the electrical side menu will cause the display of terminal symbols at these locations.

The current cell will have its own terminal locations, if any have been defined with the subct command in the side menu. These will be the connections points to instances of the current cell.

Establishing connectivity in the schematic involves logically grouping the device, subcircuit, and cell terminals that should be connected. Each such group is termed a ``net''. There are a number of ways to define this grouping.

1. Most commonly, a wire is placed by the user using the wire command in the side menu. To establish connectivity, a vertex of the wire must be at a connector hot-spot. If the dots display is enabled, a dot may be shown at the connection points.

2. Connection points whose hot-spots are placed at the same location will be connected.

These two methods illustrate connection by location. It is also possible to use connection by name. For this, one must use named nets. Looking ahead just a bit, it is possible for a net to be scalar (single conductor) or multi-conductor. The type of net is described by the name, which is interpreted as a ``net expression'', which is a syntax which allows detailed definition of the conductors in the net.

There are several ways by which a net can acquire a name.

1. Nets connected to named cell terminals will have the same name as the cell terminal, but only if the terminal has an applied name. Names can be given to cell terminals with the subct command in the side menu.

2. A scalar (single conductor) net can be assigned a name with the Node (Net) Name Mapping panel brought up with the nodmp button in the side menu. This name has priority over the ``candidate names'' applied with wire labels or terminal devices.

3. A candidate net name will be supplied by associated labels of wires in the net. A label is given to a wire through the following procedure.

• In electrical mode, select a single wire, which shall receive a name.

• Press the label button in the side menu.

• Type the label text in the prompt line, and press the Enter key.

• The label is ghost-drawn and attached to the mouse pointer. Resize or rotate the label if desired, and click in the drawing near the selected wire to place the label. This completes the operation.

4. A candidate net name can also be supplied by placing a terminal device from the device library in contact with the net. The device library provides several terminal styles. Each has a label that can be edited to apply a net name. Once placed, the label can be selected, the label button pressed, and new label text entered.

A scalar net may have multiple ``candidate names'', and each can be used to establish connections by name. However, the single name chosen to represent the net in netlist output will be the name that comes first in alphabetical order.

Nets that otherwise appear disjoint but have a common name are actually connected. This illustrates connect by name. In fact, it is possible to draw perfectly good schematics without using wires, by using terminal devices only. The schematics produced by Xic from SPICE files or physical extraction use this approach.

Xic supports multi-conductor wire nets in schematics, using a syntax and methodology that should be familiar to users of Cadence Virtuoso. The net name uses a syntax which describes the net. Unnamed nets will assume the characteristics of connected terminals.

There are three types of net.

Scalar nets
Single-conductor ``scalar'' nets provide the basic connectivity description in a schematic, and are the only electrical nets that may have a counterpart in the physical layout.

A scalar net name consists of a simple name, or an indexed vector name, in a format to be described.

Vector nets
A vector net contains multiple conductors, accessible as indices in a range, with a common base name. A name specifying a vector net may have the form
basename[start:end]

The start and end are non-negative integers. The two colon-separated numbers provides a range of subscripts which identify the individual conductors, or ``bits'', of the net.

For example, the vector net ``foo[3:0]'' consists of four conductors, in order ``foo[3]'', ``foo[2]'', ``foo[1]'', and ``foo[0]''. Note that the range values can be ascending or descending.

In Xic, the square brackets can be replaced by <...> or {...}. That is, for subscripting in Xic, square brackets, curly brackets, and angle brackets are equivalent. This documentation will use square brackets.

Vector nets differ fundamentally from scalar nets in Xic in that they simply reference scalar nets. The scalar nets actually provide the electrical connections, and the correspondence between layout and schematic. The vector and multi conductor nets in general simply provide an organizational framework for the scalar nets.

In particular, this requires that each ``bit'' of a vector net have an existing scalar net of the same name. In the example above, for the vector net foo[3:0] to be valid, the individual scalar nets foo[3] etc. must exist.

Bundle nets
A bundle net is a net of nets. Its name is a net expression consisting of comma-separated names of scalar and vector nets. Some examples would be
b0,b1,b2

These are simple cases of a net expression which describes the conductor sequence of a general net. Net expressions and vector expressions may be familiar from Cadence Virtuoso, and in fact the same operations and syntax are supported.

Next: Net and Vector Expressions Up: Electrical Schematic Editing Previous: Node and Device Naming   Contents   Index
Stephen R. Whiteley 2022-05-28