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.verilog, .endv Lines

General Form:
In WRspice, all Verilog code is placed into a block of statements starting with a line in the form
.verilog gatedly dbgflags
and ending with a .endv line. The gatedly is a word starting with `s' or `f' (case insensitive), any other word is ignored. This specifies use of slow, fast, or typical gate delays. If no such word appears, the default is typical. The dbgflags is a hex integer in C format (0xnnnn) where the nnnn is a hex number using digits 0-f. The set bits in this number correspond to the debugging flags as would be supplied in the -d option to the Whiteley Research VL Verilog simulator. See the VL documentation for information about the available flags. This feature is unlikely to be useful for most users.

The lines within Verilog block define the modules of a hierarchy, including a top-level ``stimulus'' module. This is ordinary Verilog syntax, using the subset of the complete language description that is supported by the VL simulator.

The Verilog simulation is run in parallel with transient analysis. Precisely how this occurs is controlled by the vastep option. This can be supplied on a .options line, or set as a variable before the simulation is run. The value is an unsigned integer.

The Verilog simulation is advanced by calling the vastep command, likely through a callback function called from a .stop line.

1 (the default)
The Verilog simulation is advanced at each transient analysis time step.

X (positive integer greater than 1)
The Verilog simulation is advanced after X transient time steps.

When vastep is not zero, the Verilog is actually advanced at the first time step where the simulation time is equal to or larger than the specified time. If vastep is zero, the Verilog advancement occurs when the vastep command is run, which if called from a callback will execute at the current time point. In both cases Verilog is advanced after SPICE has converged at the point.

Signals are passed to the Verilog block with .adc statements, and signals from the Verilog block are accessed through referencing voltage or current sources.

Output signals from the Verilog block are obtained through voltage or current sources in the circuit. The voltage/current source must refer by name to a Verilog variable in the scope of the top module, or use the Verilog ``dot'' path notation. The voltage/current source is set to the binary value of the variable, and has a built-in rise/fall time of one time increment. The variable reference can contain a bit or part select field.

A good primer on Verilog is: Samir Palnitkar, Verilog HDL, A Guide to Digital Design and Synthesis, SunSoft Press (Prentice Hall) ISBN 0-13-451675-3. The full story is in IEEE Standard 1364-1995.

An example input file that uses a .verilog block (ex8) is given in A.3. Other examples including prbs.cir and nor_vamc.cir are provided with WRspice.

next up previous contents index
Next: .adc Line Up: Verilog Interface Previous: Verilog Interface   Contents   Index
Stephen R. Whiteley 2022-09-18